It has long been known that semiconductor structures can be formed by patterning trenches of the desired shape on a substrate and then depositing semiconductor material to fill the trenches. US Patent Applications publication no's. 2011/0306179 and 2011/0086491 describe exemplary processes for forming III-V semiconductor structures in this way. A fundamental problem with the patterned-trench technique is that defects tend to occur in the resulting crystal structure of the semiconductor. One technique to restrict these defects, known as aspect ratio trapping (ART), involves controlling the aspect ratio of a trench defined between sidewalls of a mask such that dislocations in the semiconductor structure formed in the trench tend to terminate at the mask sidewalls. Defects are then inhibited in an upper region of the semiconductor structure above the dislocations. Examples of this type of technique are described in U.S. Pat. No. 8,324,660 and “Integration of InGaAs Channel n-MOS Devices on 200 mm Si Wafers Using the Aspect-Ratio-Trapping Technique”, Waldron et al., ECS Transactions, 45 (4) 115-128 (2012).
Defects have also been reduced in semiconductor structures using the technique of confined epitaxial layer overgrowth (ELO). With this technique, planar semiconductor structures have been grown laterally (i.e. generally parallel to the plane of the substrate) from seeds in the form of elongate stripes of monocrystalline semiconductor material. Selective epitaxial growth proceeds laterally from the seed stripes in tunnel areas defined between upper and lower confining surfaces. Examples of this technique are described in: “A New Epitaxy Technique for Device Isolation and Advanced Device Structures”, Schubert & Neudeck, Eight Biennial University/Government/Industry Symposium 1989; “Novel technique for Si epitaxial lateral overgrowth: Tunnel epitaxy”, Ogura & Fujimoto, Appl. Phys. Lett. 55, 2205 (1989); “50-nm-Thick Silicon-on-Insulator Fabrication by Advanced Epitaxial Lateral Overgrowth: Tunnel Epitaxy”, Ogura et al., J. Electrochem. Soc., Vol. 140, No. 4, April 1993; “Structural Characterization of Conformally Grown (100) Si Films”, Pribat et al., Japanese Journal of Applied Physics, Vol. 29, No. 11, 1990, pp. L1943-L1946; “Defect Filtering in GaAs on Si by Conformal Growth”, Pribat et al., Japanese Journal of Applied Physics, Vol. 30, No. 3B, 1991, pp. L431-L434; and U.S. Pat. Nos. 4,952,526 and 5,360,754. This confined ELO lateral growth technique has been used to grow planar, or two-dimensional, layer structures only.
Growth of defect-free semiconductor nanowires presents a particular challenge. Nanowires can be considered essentially “one-dimensional” structures, being elongate in form but having a transverse thickness, i.e. perpendicular to the longitudinal axis of the nanowire, of up to about 200 nm and more commonly up to about 100 nm. In many current applications, nanowire thickness is typically no greater than 100 nm. The cross-sectional shape of nanowires can vary considerably, common examples including rounded, e.g. circular, cross-sections as well as generally rectangular cross-sections giving a ribbon-shaped nanowire or “nanoribbon”. The cross-sectional dimensions, i.e. the width and breadth of the nanowire, are however usually up to about 100 nm in each case. Hence, while nanowires can typically range from nanometers to many microns in length, the cross-sectional area of a nanowire is constrained to a few tens of thousands of nm2, usually about 104 nm2 or less, and is most typically no greater than 104 nm2.
In all of the above-disclosed methods using ART or ELO, defects originating from the lattice mismatch as well as the polar/non-polar interface at the heterojunction can only be reduced and not completely avoided.
For growth of semiconductor nanowires on a substrate, a technique known as vapor-liquid-solid (VLS) deposition has been used to grow nanowires from metal catalyst particles. In “Confinement-Guided Shaping of Semiconductor Nanowires and Nanoribbons: Writing with Nanowires”, Pevzner et al., Nano Lett. 2012, 12, 7-12, this technique is used for lateral growth of nanowires from gold particles confined in tunnels on a silicon wafer. The resulting nanowires exhibit various defects. As discussed in U.S. Pat. No. 8,084,337, for example, and US Patent Application publication no. 2010/0261339, reduced defects can be achieved with this technique of growing nanowires from catalyst particles when the nanowires are grown vertically out of the substrate. “Synthesis of Vertical High-Density Epitaxial Si(100) Nanowire Arrays on a Si(100) Substrate Using an Anodic Aluminum Oxide Template”, Shimizu et al., Adv. Mater. 2007, 19, 917-920, also describes use of this technique to grow nanowires vertically from catalyst particles in a vertical nanopore array on a substrate.
Other techniques for nanowire growth are described in European Patent Application publication no. EP 2,378,557 A1, US Patent Application publication no. 2011/0253982 A1, and “Selective area growth of III-V nanowires and their hetero structures on silicon in a nanotube template: towards monolithic integration of nano-devices”, Kanungo et al., Nanotechnology 24 (2013) 225304. Again, all these documents teach vertical nanowire fabrication techniques with a view to achieving nanowires with reduced defects. In EP 2,378,557 A1, vertical nanowires are produced by removing, e.g. etching, material from a masked stack. In the Kanungo et al. paper, vertical nanowires are grown in a nanotube template structure made by coating a pre-formed sacrificial array of vertical nanowires. In US 2011/0253982 A1, a vertical III-V nanowire array is produced by direct epitaxial growth on a silicon substrate.
An improved technique for fabrication of high-quality semiconductor nanowires on substrates would be highly desirable.